1. Field of the Invention
The present invention relates to antifuses. More particularly, the present invention relates to an improved metal-to-metal amorphous silicon antifuse structure and fabrication method.
2. The Prior Art
A common problem with amorphous silicon antifuses is the high level of leakage exhibited by unprogrammed antifuses. This leakage is typically a few nanoamperes at an applied voltage of 5 volts. In isolation, such leakage exhibited by a single antifuse might be considered to be insignificant. The problem becomes apparent, however, when practical antifuse based products are considered. Large FPGA integrated circuits may employ more than one million antifuses having an aggregate leakage of a few milliamperes. This leakage rapidly worsens with temperatures, especially high temperatures of 70 to 125.degree. C. which may be encountered in FPGA arrays under normal operating conditions.
The addition of one or more layers of silicon nitride to the antifuse layer (typically'silicon nitride-amorphous silicon-silicon nitride antifuse material) does not significantly reduce this leakage. There is thus a need for an antifuse structure which avoids this problem.
In addition, a problem in antifuse arrays has been the unintended programming of antifuses during the process of programming intended antifuses. An antifuse structure which would aid in preventing the unintended programming of antifuses while substantially reducing the leakage of unprogrammed antifuses would also be desirable.
It is therefore an object of the present invention to provide an antifuse having reduced leakage in its unprogrammed state.
It is a further object of the present invention to provide an antifuse which may be disposed in an array of antifuses and which is less susceptible to unintentional programming than prior art antifuses.